1) Field of the Invention
This invention relates to a frame synchronism processing apparatus and a frame synchronism processing method suitable for use in a case wherein data transmission is carried out using a predetermined frame.
2) Description of the Related Art
A frame synchronism processing apparatus is arranged to detect information for synchronization acquisition (frame synchronism establishment) in a transmission signal (transmission frame) so that frame synchronism is established. For example, if a frame to be transmitted is a DS3 (Digital Signal-Level 3) signal, a frame synchronism processing apparatus 1a is arranged to include a DS3 subframe synchronism detecting unit (DS3 subframe Sync unit) 2a, a DS3 multiframe synchronism detecting unit (DS3 multiframe Sync unit) 3a, an OR circuit 6b, and a data inhibit/nibble switch unit (Data Inhibit+Nibble SW) 6a, as shown in FIG. 12.
It is to be noted that, as shown in FIG. 9, a frame format of a DS3 signal is formed as a DS3 multiframe which includes seven DS3 subframes each including a plurality of sets of an overhead part and a payload part. The overhead part (1 bit) in the DS3 subframes has information unique in the DS3 multiframe such as xe2x80x9cF1xe2x80x9d, xe2x80x9cF2xe2x80x9d, xe2x80x9cF3xe2x80x9d, xe2x80x9cF4xe2x80x9d, xe2x80x9cM1xe2x80x9d, xe2x80x9cM2xe2x80x9d, xe2x80x9cM3xe2x80x9d, xe2x80x9cX1xe2x80x9d, xe2x80x9cX2xe2x80x9d and so forth stored therein as seen from FIG. 9.
Here, each of xe2x80x9cF1xe2x80x9d, xe2x80x9cF2xe2x80x9d, xe2x80x9cF3xe2x80x9d, and xe2x80x9cF4xe2x80x9d is a bit representative of a synchronizing pattern of a DS3 subframe, and fixed patterns of xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are allocated to them. Meanwhile, each of xe2x80x9cM1xe2x80x9d, xe2x80x9cM2xe2x80x9d, and xe2x80x9cM3xe2x80x9d is a bit representative of a synchronizing pattern of a DS3 multiframe, and fixed values of xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are allocated to them. It is to be noted that various data are mapped in the payload part (84 bits).
Referring back to FIG. 12, the DS3 subframe synchronism detecting unit 2a detects synchronism of received DS3 subframes. In particular, the DS3 subframe synchronism detecting unit 2a detects bits (xe2x80x9cF1xe2x80x9d, xe2x80x9cF2xe2x80x9d, xe2x80x9cF3xe2x80x9d, xe2x80x9cF4xe2x80x9d) in the DS3 subframes and discriminates whether or not they coincide with the synchronizing pattern (xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d). If the DS3 subframe synchronism detecting unit 2a detects coincidence with the synchronizing pattern, then it outputs a signal indicating this to the DS3 multiframe synchronism detecting unit 3a. 
If the synchronism of the DS3 subframes is detected by the DS3 subframe synchronism detecting unit 2a, then the DS3 multiframe synchronism detecting unit 3a detects predetermined bits (xe2x80x9cM1xe2x80x9d, xe2x80x9cM2xe2x80x9d, xe2x80x9cM3xe2x80x9d) from a plurality of DS3 subframes and discriminates whether or not the detected bits coincide with the synchronizing pattern (xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d).
The data inhibit/nibble switch unit 6a inhibits outputting of data while it receives, from any one of the DS3 subframe synchronism detecting unit 2a and the DS3 multiframe synchronism detecting unit 3a through the OR circuit 6b, information (out of frame information) that synchronism cannot be detected. However, while the data inhibit/nibble switch unit 6a receives, from both the DS3 subframe synchronism detecting unit 2a and the DS3 multiframe synchronism detecting unit 3a, information that synchronism is detected (synchronous state), it extracts the payload parts except the overhead parts from the received DS3 multiframe and outputs the payload parts.
Since the frame synchronism processing apparatus 1a detects the particular bits (xe2x80x9cF1xe2x80x9d=xe2x80x9c1xe2x80x9d, xe2x80x9cF2xe2x80x9d=xe2x80x9c0xe2x80x9d, xe2x80x9cF3xe2x80x9d=xe2x80x9c0xe2x80x9d, xe2x80x9cF4xe2x80x9d=xe2x80x9c1xe2x80x9d) of DS3 subframes of a received DS3 multiframe to detect the synchronism of the DS3 subframes and then detects the particular bits xe2x80x9cM1xe2x80x9d=xe2x80x9c0xe2x80x9d, xe2x80x9cM2xe2x80x9d=xe2x80x9c1xe2x80x9d, xe2x80x9cM3xe2x80x9d=xe2x80x9c0xe2x80x9d) in the DS3 multiframe in this manner, the frame synchronism processing apparatus 1a can establish the synchronism of the DS3 frames.
FIG. 10 illustrates a method of mapping an ATM cell in a PLCP (Physical Layer Convergence Protocol) frame. As shown in FIG. 10, an ATM cell can be mapped in the payload part in a PLCP frame, and the PLCP frame can be stored into a payload part (84 bits) of a DS3 frame.
Where a PLCP frame is mapped in a payload part (84 bits) of such a DS3 frame as described above, for example, as shown in FIG. 13, the frame synchronism processing apparatus 1a further includes a PLCP frame synchronism detecting unit 4a, which in turn includes a detecting unit 4-1a, a discriminating unit 4-2a, a POI (Path Overhead Indicator) detecting unit 4-3a, a POI check unit 4-4a, a POL (Path Overhead Label)discriminating unit 4-5a, a frame pattern check unit 4-6a, and a frame counter (FCTR) 4-11a. 
It is to be noted that, for example, as shown in FIG. 11, also a frame format of a PLCP signal includes an overhead part 16 and a payload part 17. It is to be noted that reference numeral 18 denotes a trailer (stuff bits) for bit number adjustment.
Here, the overhead part 16 has framing octets (xe2x80x9cA1xe2x80x9d, xe2x80x9cA2xe2x80x9d), a POI and a POH (Path Overhead) stored therein. xe2x80x9cA1xe2x80x9d and xe2x80x9cA2xe2x80x9d are bits representative of a synchronizing pattern of a PLCP frame and have fixed values of xe2x80x9cA1xe2x80x9d=xe2x80x9cF6xe2x80x9d (hex), xe2x80x9cA2xe2x80x9d=xe2x80x9c28xe2x80x9d (hex) stored therein, respectively. Further, POI is information indicating that it is followed by a POH.
Referring back to FIG. 13, the detecting unit 4-1a detects xe2x80x9cA1xe2x80x9d and xe2x80x9cA2xe2x80x9d from the PLCP frame described above. The discriminating unit 4-2a determines whether or not xe2x80x9cA1xe2x80x9d, xe2x80x9cA2xe2x80x9d are equal to xe2x80x9cF6xe2x80x9d, xe2x80x9c28xe2x80x9d, respectively.
The POI detecting unit 4-3a detects the POI described above from a PLCP frame. The POI check unit 4-4a performs a parity check. The POL discriminating unit 4-5a determines what numbered set (slot) the set is in the entire frame. The frame pattern check unit 4-6a determines whether or not information received from the discriminating unit 4-2a, POI check unit 4-4a and POL discriminating unit 4-5a satisfies a desired requirement. The frame counter 4-11a outputs an address of a memory (not shown) into which data outputted from a byte switch 7a is to be stored after synchronism is established.
The frame synchronism processing apparatus 1a which includes the PLCP frame synchronism detecting unit 4a having such a construction as described above detects a synchronizing pattern based on the particular bits (xe2x80x9cA1xe2x80x9d=xe2x80x9cF6xe2x80x9d, xe2x80x9cA2xe2x80x9d=xe2x80x9c28xe2x80x9d) in a PLCP frame to establish the synchronism of the PLCP frame.
As described above, the frame synchronism processing apparatus 1a detects the F bits (xe2x80x9cF1xe2x80x9d, xe2x80x9cF2xe2x80x9d, xe2x80x9cF3xe2x80x9d, xe2x80x9cF4xe2x80x9d) of the DS3 frame format from received data and detects the M bits (xe2x80x9cM1xe2x80x9d, xe2x80x9cM2xe2x80x9d, xe2x80x9cM3xe2x80x9d) of the DS3 multiframe after synchronism of DS3 subframes is detected.
The received data can contain an alarm signal (ALL xe2x80x9c0xe2x80x9d) such as an AIS (Alarm Indication Signal) if a failure or the like occurs in the connection.
The F bits (xe2x80x9cF1xe2x80x9d, xe2x80x9cF2xe2x80x9d, xe2x80x9cF3xe2x80x9d, xe2x80x9cF4xe2x80x9d) which are a synchronizing pattern of DS3 subframes are disposed in a distributed condition as seen in FIG. 9, and since this synchronizing pattern is a synchronizing pattern of 4 bits, a data train same as the F bits possibly appears in received data as a result of influence of propagation of an AIS.
In this instance, although the pattern in the signal does not correspond to the original DS3 subframe synchronizing pattern, there is the possibility that the pattern is erroneously detected as the normal synchronizing pattern and a false synchronizing state is brought about.
In this case, the synchronism of the DS3 multiframe depends upon the synchronism of the DS3 subframes while the synchronism of the DS3 subframes does not depend upon the synchronism of the DS3 multi frame, if the synchronism of DS3 subframes is erroneously detected in the frame synchronous processing apparatus 1a due to a generation of AIS or the like with the result that a false synchronous state is brought about on the DS3 subframes, then the synchronism of a DS3 multiframe cannot be established, resulting in a deadlock state in the DS3 multiframe synchronism detecting unit 3a. 
Also in regard to synchronism detection of a PLCP frame, since the synchronism of the PLCP frame depends upon the synchronism of DS3 subframes, if a false synchronizing state is brought about on the DS3 subframes, then the frame synchronism processing apparatus 1a fails to establish synchronism of the PLCP frame, leading to a deadlock state.
The present invention is made in view of the above aspect and an object of the present invention is to provide a frame synchronism processing apparatus and a frame synchronism processing method in which if a false synchronous state is brought about on the synchronism of the subframe with the result that it becomes impossible to establish the synchronism on the multiframe, then synchronism detection is again carried out on each of the frames. Therefore, a deadlock caused from the false synchronous state can be avoided and reliability in processing for establishing synchronism can be improved.
In order to attain the above object, the frame synchronism processing apparatus according to the present invention is arranged to include a first detecting unit for detecting synchronism of the subframes, a second detecting unit for detecting synchronism of the multiframe after the first detecting unit detects the synchronism of the subframes, and a compulsory synchronism detection retrying control unit for compulsorily bringing the first detecting unit and the second detecting unit to a synchronism detection retrying mode if the second detecting unit fails to detect the synchronism of the multiframe after an elapse of a predetermined time after the first detecting unit has detected the synchronism of the subframes.
According to the frame synchronism processing apparatus of the present invention, even if a false synchronous state is brought about on the synchronism of the subframes due to a generation of an AIS cell or the like, with the result that the second detecting unit fails to detect the synchronism of the multiframe after the elapse of the predetermined time after the first detecting unit has detected the synchronism of the subframes, the compulsory synchronism detection retrying control unit brings the first detecting unit and the second detecting unit into the synchronism detection retrying mode. Therefore, a deadlock upon the false synchronous can be avoided and reliability in processing for establishing synchronism can be improved.
According to another aspect of the present invention, there is proposed a frame synchronism processing method comprising the steps of a first detecting step of detecting synchronism of the subframes, a second detecting step of detecting synchronism of the multiframe after the synchronism of the subframes is detected in the first detecting step, and a compulsory synchronism detection retrying step of compulsorily retrying the synchronism detection on each of the frames from the first detecting step if the synchronism of the multiframe is failed to be detected in the second detecting step after an elapse of a predetermined time after the synchronism of the subframes is detected in the first detecting step.
Therefore, according to the frame synchronism processing method of the present invention, if the false synchronous state is brought about on the synchronism of the subframe due to a generation of an AIS cell or the like, with the result that the synchronism of the multiframe is failed to be detected in the second detecting step after an elapse of the predetermined time after the synchronism of the subframes is detected in the first detecting step, the synchronism detection processing is carried out on each of the frames from the first detecting step in the compulsory synchronism detection retrying step. Therefore, a deadlock upon a false synchronous state can be avoided and the reliability in processing for establishing synchronism can be improved.
According to another aspect of the present invention, there is provided a frame synchronism processing apparatus, comprising a plurality of frame synchronism detecting units for receiving a transmission frame composed of a plurality of unit frames hierarchically arranged by nesting one another and detecting the synchronism of the unit frames at each of the hierarchies, and a compulsory synchronism detection retrying control unit for compulsorily bringing all of the frame synchronism detecting units into a synchronism detection retrying mode if the synchronism is failed to be detected by any one of the plurality of frame synchronism detecting units.
Therefore, according to the frame synchronism processing apparatus of the present invention, if a false synchronous state is brought about on any one of the unit frames due to a generation of an AIS cell or the like, with the result that any one of the plurality of frame synchronism detecting units fails to detect the synchronism, the compulsory synchronism detection retrying control unit compulsorily brings all of the frame synchronism detecting units into the synchronism detection retrying mode. Therefore, a deadlock upon a false synchronizing state can be avoided and the reliability in synchronism establishing processing can be improved.
According to a still another aspect of the present invention, there is provided a frame synchronism processing method, comprising the steps of a frame synchronism detecting step of receiving a transmission frame composed of plurality of unit frames hierarchically arranged by nesting one another and detecting the synchronism of the unit frames at each of hierarchies, and a compulsory synchronism detection retrying step of compulsorily performing the synchronism detection processing for all of the unit frames if the synchronism is failed to be detected in the frame synchronism detecting step.
Therefore, according to the frame synchronism processing method of the present invention, if false synchronous state is brought about on any one of the unit frames due to a generation of an AIS cell or the like, with the result that the synchronism of any one of the unit frames is failed to be detected in the frame synchronism detecting step, the synchronism detection processing is compulsorily performed again for all of the unit frames in the synchronism detection retrying step. Therefore, a deadlock upon a false synchronous state can be avoided and the reliability in the synchronism establishing processing can be improved.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols.